1. Field of the Invention
The present invention relates to a method of evaluating a semiconductor device, such as an evaluation of a thermal stress resistance property and the like. The present invention also relates to a semiconductor wafer having a test element.
2. Description of the Related Art
In the manufacturing process of a semiconductor device, a semiconductor chip is formed in a wafer. The semiconductor chip is diced and packaged and then shipped as a product. In order to insure that the packaged product excellently operates after the shipping, the various tests such as the temperature cycling test and the like are executed.
(A) Arranging Inhibited Region of Chip Corner
In the temperature cycling test, there is a case that a phenomenon which must be avoided in product occurs. As examples of such a phenomenon, the generation of a crack on a passivation layer and the metal interconnection slide, which are caused by temperature variation are listed. The layer crack and interconnection slide are caused by the generation of the thermal stress caused by the difference of the coefficient of thermal expansion between the passivation layer of the semiconductor chip, the metal interconnection of the semiconductor chip and the molding resin (also, there is cases of different material) covering on the semiconductor chip.
In some cases, in order to avoid such a phenomenon, the arrangement of elements and interconnections on the chip corners of the semiconductor device is inhibited. The distribution of the thermal stress on a semiconductor chip is shown in FIG. 1, in which the thermal stress is maximal in the chip corner region which is farthest from the center of the semiconductor chip. Therefore, it is possible to avoid the foregoing phenomena by employing preventive measures for inhibiting elements and metal interconnections from being arranged on the chip corners. The size of the arrangement inhibited region is determined experientially.
(B) Evaluating TEG
In order to insure that a packaged product is good, a test chip having an evaluation TEG (Test Element Group) is used. FIGS. 2, 3 show examples of the test chip formed on the wafer.
A test chip 3, which has the same size as the design size of the product semiconductor chip, is formed on the wafer 1. In the example of FIG. 2, the size of the semiconductor chip is represented by A×B (the lateral width A and the longitudinal width B). Thus, the size of the test chip 3 to evaluate the semiconductor chip is also represented by A×B. In the example of FIG. 3, the size of the semiconductor chip is represented by C×B. Hence, the size of the test chip 3 to evaluate the semiconductor chip is also represented by C×B.
In a certain stage of designing the semiconductor chip, in order to verify the property of the packaged product, the test chip adapted to the design size of the semiconductor chip in that stage is formed and mounted on the package. After the result of the evaluation for the property of this packaged test chip is checked to be good, the product semiconductor chip is packaged.
In Japanese Laid Open Patent Application JP-A-Heisei, 2-179486, a method for evaluating a thermal stress resistance property of a resin sealed type semiconductor device is described. The TEG pattern described in this document contains interconnections 101, arranged parallel to the two sides of the chip and bent at a right angle on the diagonal of the chip and repeatedly arranged at a constant pitch 105 from the chip end to the center, as shown in FIG. 4. According to this document, since the foregoing TEG chip is used, the various factors with regard to the passivation layer crack and the metal interconnection slide can be evaluated quantitatively and systematically.
In Japanese Laid Open Patent Application JP-A-Heisei, 6-5663, a test semiconductor device on which a plurality of test elements are formed is described. This test semiconductor device is characterized in that, an activated region in which the elements are formed is separated into a plurality of regions by a scribe region formed in the shape of a grid, and one or two or more bonding pads are arranged in the plurality of thus-formed regions.    (A) The arrangement inhibited region formed at the chip corner can be an obstacle for the reduction of the chip size. Thus, the arrangement inhibited region is desired to be requisite minimum size. The size of the arrangement inhibited region is desired to be quantitatively determined based on a certain data.    (B) When the test chip is used, the size of the test chip is formed in accordance with the design size of the semiconductor chip. However, there is a case that the size of the semiconductor chip is changed because of some reasons occurred in designing. Therefore, a technique is desired which enables the size of the test chip to be changed, in accordance with the design change of the semiconductor chip.